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P reli mi nary Dat a Sheet, V 0.9, Ma y 2007
TLE5010
GMR B a sed A ng u lar S en s or
Se n so rs
D
ra
ft
Edition 2007-05 Published by Infineon Technologies AG 81726 Munchen, Germany (c) 2007 Infineon Technologies AG All Rights Reserved. Legal Disclaimer The information given in this document shall in no event be regarded as a guarantee of conditions or characteristics. With respect to any examples or hints given herein, any typical values stated herein and/or any information regarding the application of the device, Infineon Technologies hereby disclaims any and all warranties and liabilities of any kind, including without limitation warranties of non-infringement of intellectual property rights of any third party. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
TLE5010 Draft Revision History: Previous Version: Page
2007-05 -
V 0.9
Subjects (major changes since last revision)
We Listen to Your Comments Any information within this document that you feel is wrong, unclear or missing at all? Your feedback will help us to continuously improve the quality of this document. Please send your proposal (including a reference to this document) to: sensors@infineon.com
Template: mc_a5_ds_tmplt.fm / 4 / 2004-09-15
TLE5010
Draft 1 1.1 1.2 1.3 1.4 2 2.1 2.2 2.3 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Target Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 6 7 7 8
2.4 3 4 5 5.1 5.2 5.3
General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Internal Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 GMR Voltage Regulator VRG (VDDG-Voltage) . . . . . . . . . . . . . . . . . 10 Analog Voltage Regulator VRA (VDDA-Voltage) . . . . . . . . . . . . . . . . 10 Digital Voltage Regulator VRD (VDDD-Voltage) . . . . . . . . . . . . . . . . 10 GMR Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Electrical and Magnetic Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . Electrical Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ESD Protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset and Amplitude . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Offset Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature dependent behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . Orthogonality Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Calibration Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Components of the Output Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Error Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature dependent Offset Value . . . . . . . . . . . . . . . . . . . . . . . . Offset Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Amplitude Normalization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Non-Orthogonality Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Resulting Angle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Anisotropy Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Hysteresis Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Residual Angle Error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GMR Parameters after Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
5.4
5.5 5.5.1 5.5.2
5.6
5.7
15 15 16 17 17 18 18 18 19 19 19 19 19 20 20 20 20 21 21 21 21 22 22 22 22 23
Preliminary Data Sheet
V 0.9, 2007-05
TLE5010
Draft 6 7 8 8.1 8.2 8.3 8.3.1 8.3.2 8.4 8.5 9 Signal Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Clock Supply (CLK Timing Definition) . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Synchronous Serial Communication Interface (SSC) . . . . . . . . . . . . . SSC Timing Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter Off . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Spike Filter On . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Filter for DATA and CS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SSC Command Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 27 27 30 30 30 31 31 32 32
Register Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Bit Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Reserved Registers (08H to 0BH) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Data Communication via SSC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . CRC Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Slave Active Byte Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Example: Update X and Y and set ADC-Test Mode . . . . . . . . . . . . . Test Structures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functional Angle Tests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ADC Test Vectors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Angle Test and Temperature Measurement Timing . . . . . . . . . . . . . . . . . Overvoltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Supply Voltage Comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD Overvoltage Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VDD - Off Comparator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 44 44 45 46 46 47 47 48 49 49 49 50 50
10 10.1 10.2 11 11.1 11.2 11.3 12 12.1 12.2 12.3 12.4 13 13.1 14 14.1
Typical Application Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Angle Sensor System . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Package Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Package Outline PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Footprint PG-DSO-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Packing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 52 53 54 54 54 55
Preliminary Data Sheet
5
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Draft
GMR Based Angular Sensor
TLE5010
1
1.1
Overview
Features
* Giant MagnetoResistance based principle * Integrated magnetic field sensing for angle measurement * Full 0 - 360 angle measurement * Highly accurate single bit SD-ADC PG-DSO-8-3 * 16 bit representation of sine / cosine values on the interface * Bidirectional SSC interface up to 2 Mbit/s * 3 pin SSC interface, SPI compatible with open drain * ADCs and filters are synchronized with external commands via SSC * Test resistors for simulating angle values * Core supply voltage 2.5 V * 0.25 m CMOS technology * Automotive qualified: -40C to +150C (Junction Temperature) * Latch up immunity according JEDEC standard * ESD > 2 kV (HBM) * Green package with lead-free plating
Type TLE5010
Marking 5010-2
Ordering Code tbd.
6
Package PG-DSO-8
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Preliminary Data Sheet
TLE5010
Draft Overview
1.2
* * * *
Target Applications
Angular position sensing in automotive applications like: Steering Angle Brushless DC Motor Commutation (e.g. EPS) Rotary Switch General Angular sensing in automotive applications
1.3
Product Description
The TLE5010 is a 360 angle sensor, which detects the orientation of a magnetic field. This is achieved by measuring sine and cosine angle components with monolithic integrated GMR elements (Giant Magnetic Resistance). Data communication is done with a bi-directional SSC interface (SPI compatible). The sine and cosine values can be read out. These signals can be digitally processed to calculate the angle orientation of the magnetic field (magnet). This calculation can be done by using a cordic algorithm. It is possible to connect more than one TLE5010 to one SSC Interface of a C for redundancy or any other reasons. In this case the synchronization of the connected TLE5010 is done by a broadcast command. Each connected TLE5010 can be addressed by a dedicated chip select CS pin. Online diagnostic functionalities are provided to ensure a reliable operation. These are * * * * Angle Test (generated via test voltages feeding the ADC). Crossed signal paths (switchable for comparison) Inverted signs of bit streams Over and undervoltage detections
Preliminary Data Sheet
7
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TLE5010
Draft Overview
1.4
Pin Configuration (top view)
8
7
6
5
Center of Sensitive Area
1
Figure 1 Table 1 Pin No. 1 2 3 4 5 6 7 8 Pin Configuration
2
3
4
Pin Definitions and Functions Symbol In/Out Function Chip Clock SSC Clock SSC Chip Select SSC Data, open drain Test Pin 1, must be connected to GND Supply voltage Ground Test Pin 2, must be connected to GND
CLK SCK CS DATA TST1 VDD GND TST2
I I I I/O I/O I/O
Preliminary Data Sheet
8
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TLE5010
Draft General
2
2.1
General
Functional Description
The clock for the sensors will be provided by external. This ensures a synchronously operation in case of multiple system participants. The sensor has its own PLL to generate the necessary clock frequency for the chip operation.
2.2
Block Diagram
The block diagram shows all switches in reset position.
GND VDD
GND-off Comp
VDD_max
TST1
VDD_O V Comp
V DD-off Comp
CLK SCK SCK
V RG VRG _OV VRG _Rst
V RA
V RA_OV
V RA_Rst
VRD
VRD_OV V RD_Rst
SSC
DA TA CS
GMR X
V DDG
Angle V oltage
Temperature Sensor
A
2
D
1
Comb Filter 16
FIR Filter 16
XH XL
GND V DDG
FS YNC
FCNT
Control FSM
A
2
D
1
Comb 16 Filter
FIR 16 Filter
YH YL
GND
GMR Y
2 differential
A ngle Voltage Analog Clock Digital Clock V RG_Rst VRA_Rst VRD_Rst Reset Lock
P LL
CLK
TLE5010
TS T1 TST2
Digital Reset
Figure 2
Block Diagram
9 V 0.9, 2007-05
Preliminary Data Sheet
TLE5010
Draft General
2.3
Internal Power Supply
The internal stages of the TLE5010 are supplied with different voltage regulators. Each voltage regulator has its own over- and undervoltage detection circuits. GMR Voltage Regulator VRG (VDDG-Voltage) The GMR voltage regulator supplies all GMR parts. * GMR Bridges * Test Voltages for Angle Test * ADC Reference Voltage The voltages are monitored in the VRG over- and undervoltage detectors. Analog Voltage Regulator VRA (VDDA-Voltage) The analog voltage regulator supplies the analog parts. * * * * * ADCs PLL (analog) VDD-Off comparator GND-Off comparator VDD Overvoltage detection
The voltages are monitored in the VRA over- and undervoltage detectors. Digital Voltage Regulator VRD (VDDD-Voltage) The digital voltage regulator supplies all digital parts. * * * * * Comb filters, FIR filters and Low Pass filter PLL (digital) Control FSM with Bitmap SSC -Interface Counters (Reset, FSYNC, FCNT)
The voltages are monitored in the VRD over- and undervoltage detectors.
Preliminary Data Sheet
10
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TLE5010
Draft General
2.4
GMR Functionality
The GMR sensor is implemented in vertical integration. This means, that the GMR active areas are integrated above the logic part. GMR elements change their resistance depending on the direction of the magnetic field. 4 individual GMR elements are connected to one Wheatstone sensor bridge. They sense either the * X component, VX (cosine) or the * Y component, VY (sine) of the applied magnetic field. The advantage of a full-bridge structure is that the GMR signal amplitude is doubled.
GMR Resistors
90
S
0
VX
VY
N
ADCX+
ADCX -
GND
ADCY+
ADCY -
V DDG
Figure 3
Sensitive bridges of the GMR Sensor1)
1)
The arrows in the resistor symbols show the direction of the reference layer
Preliminary Data Sheet
11
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TLE5010
Draft General
The output signal of each bridge is only unambiguous over 180 between two maxima. Therefore two bridges are orientated orthogonal to each other. Using the ARCTAN function, the true 360 angle value can be calculated which is represented by the relation of the X and Y signals. As only the relative values influence the result, the absolute size of the two signals is of minor importance. Therefore most influences to the amplitudes are compensated.
Y Component (SIN)
VY VX V
X Component (COS)
VX (COS)
0
90
180
270
360
Angle
VY (SIN)
Figure 4
Ideal Output of the GMR Sensor
Preliminary Data Sheet
12
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TLE5010
Draft Absolute Maximum Ratings
3
Table 2 Parameter
Absolute Maximum Ratings
Absolute Maximum Rating Parameters Symbol Limit Values min. max. 6.5 V V C mT max 5 min. @ tA = 25C max 5 h @ tA = 25C max 40 h / lifetime -0.5 -0.5 -40 Unit Notes
Voltage on VDD pin respect to ground (VSS) Voltage on any pin respect to ground (VSS) Junction Temperature
VDD VIN TJ
6.5
150 |125| |80|
VDD + 0.35 V may
not be exceeded
Magnetic Field Induction B
Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During absolute maximum rating overload conditions (VIN > VDD or VIN < GND) the voltage on VDD pins with respect to ground (GND) must not exceed the values defined by the absolute maximum ratings.
Preliminary Data Sheet
13
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TLE5010
Draft Operating Range
4
Operating Range
The following operating conditions must not be exceeded in order to ensure correct operation of the TLE5010. All parameters specified in the following sections refer to these operating conditions, unless otherwise noticed.
Table 3 Parameter
Operating Range ( - 40C < TJ < 150C ) Symbol Limit Values min. typ. -5 30 max. 5.5 -10 5.5 45 360 50 15 V mA V mT C Years
1) 2) 3)
Unit
Notes
Supply Voltage Output Current Input Voltage
VDD IQ VIN
4.5 -0.3 25 0 -40 -
VDD + 0.5 V may not
be exceeded In X / Y direction4) sine / cosine
Magnetic Induction BXY Angle Range Storage Temperature Overall Life Time
1) 2) 3)
Ang TST tlife
Directly blocked with 100 nF ceramic capacitor Max current to GND over Open Drain Output The corresponding voltage levels are listed in Table 5 "Electrical Parameters for 4.5V < VDD < 5.5V" on Page 16 Values refer to an homogenous magnetic field (Bxy) without vertical magnetic induction (Bz = 0 mT). By applying a vertical magnetic induction an additional error has to be considered
4)
Note:
For a calculation of the corresponding ambient temperature the thermal resistances in Table 20 "Package Parameters" on Page 51 have to be used.
Preliminary Data Sheet
14
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TLE5010
Draft Electrical and Magnetic Parameters
5
5.1
Electrical and Magnetic Parameters
Electrical Parameters
These are all parameters over operating range, unless otherwise specified. Unless individually specified, typical values correspond to a supply voltage VDD = 5.0 V and 25C. All other values correspond to - 40C < TJ < 150C Table 4 Parameter Supply Current POR Level POR Hysteresis Power On Time PLL Jitter ADC Noise 5) Input Signal Low Level Input Signal High Level Capacitance of SSC Data Pin
1) 2) 3) 4) 5)
Electrical Parameters Symbol Limit Values min.
1)
Unit max. 20 21 2.9 200 2.0 2) 3.9 2.2 4.42) 0.3 VDD VDD +0.35 6 2) V V pF V mV s ns mA
Notes
typ. 15 2.3 30 100 1.3 3.0 1 2 4
IDD
-
VDD = 4.5 to 5.5V VDD = 6.5 V
Power On Reset
VPOR 2.0 VPORhy tPon 50 tPLLjit_S tPLLjit_L NADC -
VDD > VDDmin & after first edge on fCLK
short term
3)
long term 4) digits 1 @ FIR_BYP = 0 1 @ FIR_BYP = 1 Tested only at DATA pin as structures of all pins are identical Internal
VL VH
-0.35 0.7 VDD
CLDATA -
Without external pull-up resistor for SSC-Interface Not tested From pulse to pulse Accumulated over 1 ms ADC noise in respect to the peak ADC value specified in "Signal Processing" on Page 23. Noise tested using 1 of 100 sample values from Angle Test "000"
Preliminary Data Sheet
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TLE5010
Draft
..
Electrical and Magnetic Parameters Electrical Parameters for 4.5V < VDD < 5.5V Symbol Limit Values min. typ. max. -150 225 225 150 0.7 0.4 V V A A 0.07 VDD -10 15 15 10 Unit Notes
Table 5 Parameter
VHY Pull-Up Current IPU Pull-Down Current IPD
Input Hysteresis
CS, DATA
SCK, CLK TST1 TST2
Output Signal Low Level
1)
VOL
-
IQ = - 10 mA IQ = - 5 mA 1)
The value -5 mA is not tested
5.2
Table 6 Parameter
ESD Protection
ESD Protection Symbol Limit Values min. max. 2 500 kV V HBM 1) CDM
2)
Unit
Notes
ESD Voltage
1) 2)
VHBM VCDM
-
Human Body Model (HBM) according to: JEDEC EIA/JESD22-A114-B (R = 1.5 k, C = 100 pF, TA = 25C) Charge Device Model (CDM) according to: ANSI ESD STM JEDEC JESD 22-C101-A Class III.
Preliminary Data Sheet
16
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TLE5010
Draft Electrical and Magnetic Parameters
5.3
Table 7 Parameter
GMR Parameters
Basic GMR Parameters Symbol Limit Values min. typ. 12337 100 0 max. 23230 digits 15781 20620 120 3000 10.0 5000 % digits @ Calib. Conditions Operating Range @ Calib. Conditions @ Calib. Conditions digits @ Calib. Conditions Unit Notes
All parameters over operating range, unless otherwise specified.
X, Y Output range X, Y Amplitude
1)
RGADC AX, AY 7402
3922 80 -10.0 -5000 -
X, Y Synchronism 2) k X; Y Offset
3)
OX, OY
-3000 0
X, Y Orthogonality Error X,Y without field
1) 2) 3) 4)
X0, Y0
digits without magnet4)
See Figure 4, Page 12
k = 100 x ( AX / AY ). OSIN = ( YMAX + YMIN ) / 2 ; OCOS = ( XMAX + XMIN ) / 2
Not tested.
Offset and Amplitude
VY
+A 0 0 -A 90 180 270 360
Offset
Angle
Figure 5
Offset and Amplitude Definition
Preliminary Data Sheet
17
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TLE5010
Draft Amplitude Definition The amplitude is defined as half difference between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave. Electrical and Magnetic Parameters
X MAX - X MIN A X = -------------------------------AY
Offset Definition The offset of the X and Y signals is defined as the mean value between the signed maximum and minimum values of the idealized (fitted) sine or cosine wave.
2 Y MAX - Y MIN = -------------------------------2
X MAX + X MIN O X = --------------------------------OY
Temperature dependent behavior The temperature offset gradients for both channels depend on the value at 25C. It can be calculated using following linear equations:
2 Y MAX + Y MIN = -------------------------------2
KT OX = tco_d_x + ( tco_k_x x O X25 ) KT OY = tco_d_y + ( tco_k_y x O Y25 )
OX25, OY25: Offset values at 25C in digits.
. Table 8 Parameter Offset Temperature Coefficient base Offset Temperature Coefficient gain GMR Temperature Coefficients Symbol Limit Values min. typ. +0.116296 -0.079401 -0.0010147 -0.0010121 max. 1_/_K digits_/_K Unit Notes
tco_d_x tco_d_y tco_k_x tco_k_y -
Preliminary Data Sheet
18
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TLE5010
Draft Orthogonality Definition The corresponding maximum and zero crossing points of the SIN and COS signals are not exactly in a distance of 90. The difference between X and Y phase is called 'Orthogonality Error'. Electrical and Magnetic Parameters
= X - Y
jideal = 0 jX : Phase error of X (= cos) Signal jY : Phase error of Y (= sin) Signal
5.4
Calibration
GMR Values The end-of-line calibration can be done using following sequence. The conditions are specified in Table 9. * * * * * * Turn magnetic field left and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of left turn Turn further 90 left and 90 back right without measurement Turn magnetic field right and measure X and Y values Calculation of Amplitude, Offset, Phase correction values of right turn Calculation of mean values of Amplitude, Offset, Phase correction values
The above gained values have to be stored in a non-volatile memory. They are used for the correction of the read-out X and Y values before the angular calculation. The resulting angular deviation is calculated using above determined parameters. Temperature Measurement The signal amplitude T25 of the temperature measurement path at calibration conditions has to be measured and stored. Calibration Conditions All errors are related to a calibration done using following conditions: Table 9 Parameter Flux density Temperature GMR calibration conditions Symbol Limit Values min. typ. 30 25 max. mT C Unit Notes
BCAL TCAL
-
BZ = 0 mT
Preliminary Data Sheet
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Draft Electrical and Magnetic Parameters
5.5 5.5.1
Angle Calculation Components of the Output Signals
The X and Y signals at the output can be described with following equations:
X = A X x cos ( + X ) + O X Y = A Y x sin ( + Y ) + O Y
AX : Amplitude of X (= cos) Signal OX : Offset of X (= cos) Signal
X : Phase error of X (= cos) Signal
AY : Amplitude of Y (= sin) Signal OY : Offset of Y (= sin) Signal
Y : Phase error of Y (= sin) Signal
5.5.2
GMR Error Compensation
Temperature dependent Offset Value To increase the accuracy, the temperature dependent offset drift can be compensated. The temperature of the chip has to be read out. The Offset values OX and OY have to be multiplied with the Offset temperature coefficient and the temperature value.
O X = O X25 + ------------- x ( T - T 25 ) S
T
KT OX
O Y = O Y25 + ------------- x ( T - T 25 ) S
T
KT OY
OX25 , OY25 : Offset value at 25C in digits T25 : Temperature value at 25C in digits T : Temperature value in digits ST : Sensitivity of the temperature measurement path, (see chapter "Temperature
Measurement" on Page 46).
Preliminary Data Sheet
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TLE5010
Draft Offset Correction After read-out of the X and Y value first the temperature corrected offset value has to be subtracted. Electrical and Magnetic Parameters
X 1 = X - OX Y1 = Y - OY
Amplitude Normalization Then the X and Y values are normalized using the peak values determined in the calibration.
X1 X 2 = -----AX
1 Y 2 = ------
Y
AY
Non-Orthogonality Correction The influence of the non-orthogonality can be compensated using following equation. Only the Y channel has to be corrected.
Y 3 = -----------------------------------------cos ( - )
Resulting Angle After correction of all errors, the resulting angle can be calculated using the arctan function1).
Y 2 - X 2 x sin ( - )
Y3 = arc tan ------ - X X 2
1)
C-function "arctan2(Y3,X2)" to resolve 360
Preliminary Data Sheet
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TLE5010
Draft Electrical and Magnetic Parameters
5.6
GMR Parameters after Calibration
After calibration under the conditions specified in Table 9 "GMR calibration conditions" on Page 19, the sensor has following remaining error: The error value refers to BZ = 0 mT and operating conditions given in Table 3 "Operating Range ( - 40C < TJ < 150C )" on Page 14. Table 10 Parameter GMR parameter with temperature dependent offset compensation Symbol Limit Values min. typ.
1)
Unit Notes max. 2,0
2) 3)
Overall Error
1) 2) 3)
-
0.7
At 25C, B=30mT incl. hysteresis error At 0h
Preliminary Data Sheet
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TLE5010
Draft Signal Processing
6
Table 11 Parameter
Signal Processing
Signal Processing Symbol Limit Values min. typ.1) 4.9 19.6 max. kHz FIR_BYP=0 FIR_BYP=1 23230 s FIR_BYP=0 FIR_BYP=1 FIR_BYP=0 FIR_BYP=1 digits signed 16 bit integer (2s complement) 4) 5)
6)
Unit
Notes
Internal Cutoff Frequency (-3dB) of sin or cos Value Update Time of sin or cos Value2) Settle Time
3)
fCut-Off
-
tupd
-
81,9 20,5 163,8 41,0 -
tsettle ADCPk
-
Peak ADC Output value
1) 2)
For 4 Mhz input frequency tupd = 8192 / (25 x fCLK) for FIR_BYP = 0 tupd = 8192 / (100 x fCLK) for FIR_BYP = 1 tsettle = 2 x tupd , after change of ADC input source Output values are valid up to this limit. Above it, corrupted results may occur due to non-linearity of the ADC. The internal quantization is typically 5.166 V per digit. Correspond to max. GMR output value.
3) 4) 5) 6)
Preliminary Data Sheet
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Draft Clock Supply (CLK Timing Definition)
7
Clock Supply (CLK Timing Definition)
The clock signal input "CLK" must fulfill certain requirements which are described in the following: * The high or low pulse width must not exceed the specified values, because the PLL needs a minimum pulse width and must be spike filtered. * The duty cycle factor should be 0.5 but can deviate to the values limited by tCLKh(f_min) and tCLKl(f_min). * The PLL is triggered at the positive edge of the clock. If more than 2 edges are missing, a chip reset is generated automatically.
tCLK tCLKh tCLKl VH VL t
Figure 6 CLK Timing Definition
Table 12 Parameter
CLK Timing Specification Symbol Limit Values min. typ. 4.00 50 100 25 40 max. 4.2 70 20 20 MHz % ns ns MHz MHz ns from VL to VH from VH to VL 3.9 30 Unit Notes
fCLK CLK Duty Cycle CLKDUTY CLK rise time tCLKr CLK fall time tCLKf PLL Frequency fPLL Digital Clock fDIG Digital Clock Periode tDIG
Input Frequency
1)
1)
fCLK * 25
( 25 / 4 ) * fCLK 4 / (25 * fCLK)
Minimum duty cycle factor: tCLKh(f_min) / tCLK(f_min) with tCLK(f_min) = 1 / fCLK(f_min) Maximum duty cycle factor: tCLKh(f_max) / tCLK(f_min) with tCLKh(f_max) = tCLK(f_min) - tCLKl(min)
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
8
Synchronous Serial Communication Interface (SSC)
The 3 pin synchronous serial interface (SSC) has a bidirectional data line (open drain), serial clock signal and chip select. It is designed to communicate with a micro controller with bidirectional SSC interface supporting Open Drain. Other micro controllers may require an external NPN transistor. This allows communication with SPI compatible devices.
C (SSC Master)
Shift Register
DATA *)
typ. 1k *)
TLE 501x (SSC Slave)
DATA
Shift Register
SCK
*) SCK *) CS
Clock Generator
Figure 7
CS *) optional , e.g. 100
SSC Half-Duplex Configuration for C with Open Drain support
C (SSC Master)
Shift Register
typ. 1k MRST MTSR optional *) SCK *) CS *) optional , e.g. 100 SCK CS *) *) DATA
TLE 501x (SSC Slave)
Shift Register
Clock Generator
Figure 8
SSC Half-Duplex Configuration for C without Open Drain support
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
8.1
SSC Timing Definition
SSC Timing Diagram
tSCKp tCSs CS SCK tSCKh tSCKl
tCSh
tCSoff VH VL VH VL VH VL
DATA tDATr tDATw
Figure 9
SSC Timing Definition
* SSC Inactive Time ( CSoff ) The SSC inactive time defines the delay, before the TLE5010 can be selected again after a transfer. The TLE5010 reacts only to one command after SSC inactive time. Then the SSC Interface of the TLE5010 is disabled until the next SSC Inactive Time is performed. * DATA Write Time ( tDATW ) During this time the TLE5010 changes the data line, thus the data are invalid. The DATA Write Time values are defined without pull-up resistor. * Pull-up Time Value ( tPU ) The value in Table 13 "SSC Timing Specification" on Page 27 is estimated with 60 ns. * Chip Select Off time ( tCSOFF )
Preliminary Data Sheet
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Draft Table 13 Parameter SSC Baud Rate CS Setup Time Synchronous Serial Communication Interface (SSC) SSC Timing Specification 1) Symbol Limit Values min. typ. max. 2.0 2.12) 7*tDIG+10 7*tDIG+10 7*tDIG+50 + tPU 30 4) ns MBit / s ns ns ns ns ns ns SSC_FILT = 0 SSC_FILT = 1 SSC inactive time Unit Notes
fSSC
-
tCSs CS Hold Time tCSh CSoff tCSoff SCK High tSCKh SCK Low tSCKl DATA Read Time tDATr
(Data Valid Time) DATA Write Time (Data Valid Time)
3)
3*tDIG+10 5*tDIG+10 10*tDIG 5*tDIG 5*tDIG 6*tDIG-10 5*tDIG-10 -
tDATw
6*tDIG+25 -
DATA slope
1) 2) 3) 4) 5)
tDATs
-
20
ns
Falling edge 5)
Timings have to be calculated acc. Table 12 "CLK Timing Specification" on Page 24. fCLK/2, synchronized to fCLK if fCLK = fCLK(max)
tPU is the time generated by the pull-up resistor
Not tested. Internal slope control of falling edge for data bit transition from VH to VL.
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
t SCKl MIN t SCKh
SCK
t DATw MIN
S SC_FILT=0
t DATw MAX
Wr
tPU
Earliest sample timepoint
t DATr MIN t DATr MAX
Rd
SCK
t DATw MIN t DATw MAX
Wr
tDATr MIN
tPU
SSC_FILT=1
Earliest sample timepoint of second sample from 2 of 3 filter
t DATr MAX
Rd
Figure 10 Note:
SSC Interface Timing Details with worst-case specified Timing
- The read window includes the sampling of the data bit. - For SSC_FILT = 1, the 2-of-3 selection is already regarded. Only the 2 last data values have to be equal. - For SSC_FILT = 0 only one sample point is selected.
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
The margin time in following table is the time between write access to the SSC Data Line and the earliest possible sample read of the TLE5010 itself for read back. It is useful to have a maximum distance between WRITE and subsequent READ. This ensures a reliable read back of the written data for the Slave-Active Byte generation. Table 14 Maximum Pull-up Time Margin with worst-case specified Timing SSC_TIMING don't care Min. tPU Margin 1) 90 50 Unit ns Comment SSC_FILT 0 1
1)
Calculation: Margin=tSCKl(min)+tDATwMAX -(tPU)-tDATrMIN.For Margin<50 ns no problems can occur.
8.2
SSC Baud rate
The SSC Baud rate depends on the internal clock frequency. 12 internal digital clock cycles are necessary to ensure a reliable operation. Therefore the maximum SSC Baud rate depends on the external CLK.
f CLK f SSC = ----------
2
8.3
SSC Spike Filter
A SSC Spike Filter for all SSC lines can be selected via the SSC_FILT bit.
8.3.1
SSC Spike Filter Off
When the spike filter is disabled, each slope of a rising voltage is used to define a bit. This is independent of the length of the sampled pulse. For example a positive spike generates therefore a rising and a falling edge.
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
8.3.2
SSC Spike Filter On
A sliding window with four consecutive sample bits is analyzed. The sample frequency is:
f S = -------------f DIGIT
Rising Edge Detect for SCK * After a rising edge (LH combination), at least one of the 2 following samples has to be 'high'. Valid bit combinations: 0111 , 0110 , 0101. * A falling condition has to be detected before. Falling Edge Detect for SCK * After a falling edge (HL combination), at least one of the 2 following samples has to be 'low'. Valid bit combinations: 1000 , 1001 , 1010. * A rising condition has to be detected before.
1
SCK (PAD)
SCK Fall
Suppressed Spike SCK rise detected
SCK fall detected
SCK Rise
Masked, because no fall detected
Figure 11
SSC Spike Filter
Filter for DATA and CS * The DATA pin has a '2-of-3' filter. * The CS input has a '2-of-3' filter, which suppresses only positive spikes.
Preliminary Data Sheet
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Draft Synchronous Serial Communication Interface (SSC)
8.4
* * * *
SSC Data Transfer
The following transfer bytes are possible: Command byte (to access and change operating modes of the TLE5010) Data bytes (any data transferred in any direction) CRC byte (cyclic redundancy check) Slave Active byte (response of all selected slaves)
SSC-Master is driving DATA (C)
SSC-Slave is driving DATA (Sensor)
Command Byte SCK DATA CS
MSB 6 5 4 3 2 1 LSB MSB 6 5
Data Byte(s)
4
3
2
1
LSB
DATA
Command Byte
Data
CRC
SlaveActive
SSC-Master is driving DATA (C)
SSC-Slave is driving DATA (Sensor)
Figure 12
SSC Data Transfer (Data Read Example)
8.5
SSC Command Byte
The TLE5010 is controlled by a command byte. It is sent first at every data transmission. Table 15 Name RW ADDR ND Structure of the Command Byte Bits [7] [6..3] [2..0] Description Read - Write '0' = write, '1' = read Address to be read / written '0..15' - register start address (address auto increment) Number of data bytes '0..7' - number of data bytes to be transferred
Preliminary Data Sheet
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TLE5010
Draft Register Table
9
Register Table
This chapter defines the complete address range as well as all registers of the TLE5010. It also defines the read/write access rights of the specific registers. In the following table values through symbols are listed. Access to the registers is done via the SSC interface. Table 16 Addr. Name Address Map Bits 7 6 5 4 3 2 SSC_ FILT XLow XHigh YLow YHigh STAT_ GMR_ UPDATE VR OFF FSYNC ANGT_ EN ANGT_Y reserved reserved reserved reserved FILT_ FILT_ CRS BYP LOCK VRG_ VRA_ OV OV ANGT_X FCNT 1 0
00H 01H 02H 03H 04H 05H 06H 07H 08H 09H 0AH 0BH 0CH 0DH 0EH 0FH
CTRL1
AUTO UR
XL XH YL YH FCNT_ STAT FSYNC_ FILT_ INV INV ANGT TST ID LOCK CRTL2 -
TEMP_ FILT_ ADCPY EN PAR DEV_ID VDD_ OV VDD_ OFF GND_ OFF
TST_ TST_ TST_ ADC GMR CHAN REV_ID VRD_ OV
S_NO
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Draft Bit Types Abbreviation L Function Locked Description Locked register. These registers can only be written, when the unlockvalue is written in the lock register (0EH). This ensures, that these bits cannot be modified unwanted during normal operation. Update-Buffer is for this bit is present. In case of an Update Command and the UpdateMode bit (UR in CTRL1) is set, the immediate values are stored in this Update-Buffer simultaneous. This enables a snapshot of all necessary system parameters at the same time. Reset only after readout Read-only registers Read and write registers Register Table
U
Update
S R W
Status Read Write
Preliminary Data Sheet
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Draft CTRL1 Addr: 00H
7 reserved 6 reserved 5 reserved 4
Register Table
Reset Value: 01H
3 2 1 AUTO WL 0 UR WL
reserved SSC_FILT reserved WL WL -
Field reserved reserved reserved reserved SSC_FILT
Bits 7 6 5 4 3
Type WL
Description reserved, has to be set to 0 reserved, has to be set to 0 reserved, has to be set to 0 reserved, has to be set to 0 SSC Digital Spike Filter enable for all SSC lines ( CS, CLK and DATA ) 0: Digital SSC Spike filters off 1: Digital SSC Spike filters on (modified timing) reserved, has to be set to 0 Automatic update at angle tests 0: no automatic update in Angle Test Mode 1: automatic update-command after tsettle, counters FSYNC and FCNT are reset to "0". Then the Angle-Test (ANGT_EN) is automatically disabled and switches back to normal operation. Also the UPDATE bit is toggled Update / Run Mode 0: Run Mode (Buffer1 values are immediate values) 1: Update Mode (Buffer2 values are stored values)
reserved AUTO
2 1
WL
UR
0
WL
Preliminary Data Sheet
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Draft Register Table
The values in Register 01H to 04H represent one byte of two's complement signed 16 bit integer values. X_L Addr: 01H
7 6 5 4
Reset Value: 00H
3 2 1 0
X Low Byte RU
X_H Addr: 02H
7 6 5 4
Reset Value: 00H
3 2 1 0
X High Byte RU
Y_L Addr: 03H
7 6 5 4
Reset Value: 00H
3 2 1 0
Y Low Byte RU
Y_H Addr: 04H
7 6 5 4
Reset Value: 00H
3 2 1 0
Y High Byte RU
Preliminary Data Sheet
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Draft FCNT_STAT Addr: 05H
7 reserved 6 5 4
Register Table
Reset Value: 80H
3 2 FCNT RU 1 0
STAT_VR GMR_OFF UPDATE RS RU RS
Field reserved STAT_VR
Bits 7 6
Type RS
Description Voltage Regulator Status This bit is a logical OR combination of Digital, Analog, GMR and VDDOV Comparator and GNDOFF, and VDDOFF Comparator outputs. 0: Voltage Supply ok 1: Voltage Supply not ok ADC Values are no GMR values (e.g.: Temperature measurement is active) This bit indicates, whether GMR values or any other values are connected to the ADCs. This value is read back from the multiplexer control signals. 0: X,Y Values are GMR values 1: X,Y Values normally represent temp. measurement or angle test values. In case of non functional MUX this bit is set to "1" Update Toggle bit. This bit toggles after every update (update command or automatic update at angle test) The bit is independent of 'UR' bit in CTRL1 Frame Counter (4 bit unsigned integer value) This counter counts every new X,Y value pair coming out of the data path. (approx. 80s) This counter is reset to 0H after any write to FSYNC and after every change of the ANGT_EN bit. As tsettle time has to be waited for valid X,Y data, this counter must be 2H to indicate valid X,Y values. If it overflows, it resets to 3H to show, that values are still valid. Note: If FIR_BYP is activated, this counter counts 4 times faster!
GMR_OFF
5
RU
UPDATE
4
RU
FCNT
3-0
RU
Preliminary Data Sheet
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Draft FSYNC_INV Addr: 06H
7 FILT_INV WU 6 5 4
Register Table
Reset Value: 00H
3 FSYNC WU 2 1 0
Field FILT_INV
Bits 7
Type WU
Description Filter Input Inversion (to check the digital data path during operation) 0: Filter Inputs are not inverted 1: Filter Inputs are inverted Frame Synchronization (7bit unsigned integer value) The Filter Update time of approx. 80 s results from the filter decimation. The phase of this decimation can be set and checked by this counter. If FIR_BYP is activated, this counter overflows at the value 31D.
FSYNC
6-0
WU
ANGT Addr: 07H
7 6 5 4 ANGT_Y W
Reset Value: 00H
3 2 1 ANGT_X W 0
reserved ANGT_EN W
Field reserved ANGT_EN
Bits 7 6
Type W
Description reserved, has to be set to 0 Angle Test Enable 0: Angle Test disable command 1: Angle Test enable command in this case X and Y values represent resistive test values, which can be used to simulate angle values Angle Test X and Y value see : Table 17 "Functional Angle Test" on Page 45
ANGT_Y ANGT_X
5-3 2-0
W W
Preliminary Data Sheet
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Draft Reserved Registers (08H to 0BH) The values in these registers are 8 bit unsigned integer values. The values in addr.8 and addr.9 have to be in reset status. Reserved Addr: 08H
7 6 5 4 Reserved
Register Table
Reset Value: FFH
3 2 1 0
Reserved Addr: 09H - 0BH
7 6 5 4
Reset Value: 00H
3 Reserved 2 1 0
Preliminary Data Sheet
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Draft TST Addr: 0CH
7 TEMP_EN 6 ADCPY 5 4
Register Table
Reset Value: 00H
3 2 1 0 TST_ CHAN
FILT_PAR FILT_CRS FIR_BYP
TST_ADC TST_GMR
WL Field TEMP_EN
WL Bits 7
WL Type WL
WL Description
WL
WL
WL
WL
Temperature Device Enable 0: Temperature Measurement disabled 1: Temperature Measurement enabled The X value represents the temperature. Automatic update mode enabled, if AUTO='1' Y Polarity 0: No inversion of Y bit stream 1: Inversion of Y bit stream (rotating direct. changed) Filter switched parallel 0: Filters in normal mode 1: Filters parallel, input selected by TST_CHAN Filter switched across 0: Filters in normal mode 1: Filters crossed, X and Y outputs are exchanged FIR Filter Bypass 0: No FIR Bypass 1: FIR Bypass ADC input switch to TST1and TST2 0: No ADC input switch, normal operation 1: ADC input switched to TST1,2, ADC selected by TST_CHAN 2) GMR switch to TST1and TST2 0: No GMR switch, normal operation 1: GMR switched to TST1,2 2) Test Channel select 0: X channel linked to TST1and TST2 1: Y channel linked to TST1and TST2
ADCPY
6
WL
FILT_PAR
5
WL
FILT_CRS
4
WL
FIR_BYP
3
WL
TST_ADC 1)
2
WL
TST_GMR 1)
1
WL
TST_CHAN
0
WL
1) 2)
Only for test purposes if TST_ADC and TST_GMR are set to '1' at the same time, TST_GMR is forced to 0. TST_ADC has the higher priority.
Preliminary Data Sheet
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Draft ID Addr: 0DH
7 6 DEV_ID R 5 4
Register Table
Reset Value: 12H
3 2 DEV_REV R 1 0
Field
DEV_ID
Bits 7-4
Type
R
Description Device Identifier 001H: TLE5010 productive chip Device Revision (current number) 00H: TLE5010 productive chip, 1st revision (B11) 01H: TLE5010 productive chip, 2nd revision (B21) 02H: TLE5010 productive chip, 3rd revision (B31) 03H: TLE5010 productive chip, 4th revision (B41) (Referred to errata sheets for further versions)
DEV_REV
3-0
R
LOCK Addr: 0EH
7 6 5 4
Reset Value: 00H
3 LOCK W 2 1 0
Field LOCK
Bits 7-0
Type W
Description Lock Byte 5AH: Lock registers locked = 5AH: Lock registers unlocked
CTRL2 Addr: 0FH
7 VDD_OV RS 6 5 4
Reset Value: 00H
3 VRA_OV RS 40 2 VRD_OV RS 1 S_NO WL V 0.9, 2007-05 0
VDD_OFF GND_OFF VRG_OV RS RS RS
Preliminary Data Sheet
TLE5010
Draft Field VDD_OV Bits 7 Type RS Description VDD Overvoltage Comparator 0: No VDD Overvoltage occurred 1: VDD Overvoltage occurred Register Table
VDD_OFF
6
RS
VDD - Off Comparator 0: No VDD - Off occurred 1: VDD - Off occurred
GND - Off Comparator 0: No GND - Off occurred 1: GND - Off occurred GMR Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRG Overvoltage occurred Analog Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRA Overvoltage occurred Digital Voltage Regulator Overvoltage Comparator 0: Voltage ok 1: VRD Overvoltage occurred Slave Number Used in the SSC protocol
GND_OFF
5
RS
VRG_OV
4
RS
VRA_OV
3
RS
VRD_OV
2
RS
S_NO
1-0
WL
Preliminary Data Sheet
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Draft Data Communication via SSC
10
Data Communication via SSC
* The data transmission order is 'MSB first'. * Data is put on the data line with the rising edge on SCK and read with the falling edge on SCK. * The SSC interface is byte aligned. Functions are activated after each transmitted byte. * A "high" condition on the negated chip select pin (CS) of the selected TLE5010 interrupts the transfer immediately. The CRC calculator is automatically resetted. * Every access to the TLE5010 with ND (number of data) 1 is done with address auto increment. * After an auto-increment overflow the addresses are beginning from 00H again. * For every data transfer with ND 1 a 8 bit CRC byte will be appended by the selected TLE5010. No CRC byte is sent in a data transfer with ND = 0 (e.g. Update Command). * After the CRC byte is sent, the bit represented by S_NO is pulled low by the selected slave in the Slave-Active-Byte (bits [3..0], low nibble). In this way, also broadcastmessages produce an individual feedback of every selected slave. This is necessary to differentiate the individual TLE5010 slave response, because the CRC byte is written by both TLE5010 in parallel. * If the CRC byte on the bus is the same as the internal generated CRC of each TLE5010, each slave pulls low the dedicated bit in the Slave-Active-Byte (bits [7..4], high nibble). If not, the bit in the high nibble remains '1'. * A write command to address 00H with ND = 0 will update all values inside the TLE5010, and only in this case the transfer can proceed. Furthermore this command is add to the CRC-calculation of the following SSC Transfer. * A command of "0000_0000" is called 'Update Command'. This command transfers the present immediate values of each register to the update register. After an Update Command, the CS line need not set and reset again. * After the CRC and Slave-Active byte have been sent the transfer ends. The TLE5010 always sends logical "1" and all following sent bits from the SSC Master are ignored (TLE5010 is in idle mode). To enable data transfers again the chip select pin (CS) of the TLE5010 has to be deselected for CSoff (see Table 13) once. * If the update mode is selected (CTRL register, UR = '1'), all accesses are done to update registers where update registers are present. Other registers are accessed directly.
Preliminary Data Sheet
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Draft Data Communication via SSC
10.1
CRC Generation
* This CRC is according to the J1850 Bus-Specification of 15.Feb.1994 for Class B Data Communication. * Every new transfer resets the CRC generation. * Every byte of a transfer will be taken into account to generate the CRC (also the sent command(s)). * Generator Polynom: X8+X4+X3+X2+1, for the CRC generation the fast CRC generation circuit is used. (See Figure 13) * The remainder of the fast CRC circuit is initial set to '11111111B'. * Remainder is bit inverted before transmission.
Figure 13 shows the fast CRC Polynom. The zero extension for initial CRC calculation is included!
Input
xor
&
1
X0
1
X1
xor
1
X2
xor
1
X3
xor 1 X4
1
X5
1
X6
1
X7
TX_CRC
Serial CRC output
parallel Remainder
Figure 13 Fast CRC polynomial division circuit
10.2
Slave Active Byte Generation
The position of the '0' in a nibble corresponds to the given slave number. The slave active byte (cccc_nnnn) is made up of a * low nibble (nnnn). One '0' is generated always according to the slave number. * high nibble (cccc). The '0' is only generated, if the readback CRC is correct. Slave1: S_NO = 0 Slave2: S_NO = 1 Slave3: S_NO = 2 Slace4: S_NO = 3 bit 0 is pulled low bit 1 is pulled low bit 2 is pulled low bit 3 is pulled low Slave Active Byte: 1110_1110 Slave Active Byte: 1101_1101 Slave Active Byte: 1011_1011 Slave Active Byte: 0111_0111
Example for a communication disturbed by other bus participants:
Slave1: S_NO = 0 bit 0 is pulled low, but the high nibble remains as '1111'. > Slave Active Byte: 1111_1110
Preliminary Data Sheet
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TLE5010
Draft Example: Update X and Y and set ADC-Test Mode Command 00000001 Data 00000101 CRC (init all `0') 00000000 Data Communication via SSC
----------------------------------xor 11111111 -------=11111110.0 . .A xor 10001110.1 . . --------.. . = 01110000.10 . .B xor 1000111.01 . . -------.-. . = 0110111.110 . .C xor 100011.101 . . ------.--. . = 10100.0110 . .D xor 10001.1101 . . -----.---. . = 00101.101101 . .E xor 100.011101 . . ---.------ . . = 001.11000001. .F xor 1.00011101. . ---.------ . . =.11011100.0 .G xor.10001110.1 . .--------.. = 1010010.10 .H xor 1000111.01 . -------.. = 10101.1100 .I xor 10001.1101 . ----.----. = 100.000100 .J xor 100.011101 . ---.------ . =01100100. Remainder 10011011 inverted Remainder Transmitted Sequence: Command Data CRC 00000001 00000101 10011011
Preliminary Data Sheet 44 V 0.9, 2007-05
TLE5010
Draft Test Structures
11
Test Structures
Two different test signal structures are implemented in the TLE5010. These are: * Functional angle test. In this case, well-knows signals feed the ADCs. * Temperature measurement. This is useful to read out the chip temperature for compensation purposes.
11.1
Functional Angle Tests
It is possible to feed the ADCs with appropriate values to simulate a certain magnetposition and other GMR effects. The values are generated with resistors on the chip. Following X / Y ADC values can be programmed: * 4 points, circle amplitude = 70.7% (0, 90, 180, 270) * 8 points, circle amplitude = 100.0% (0, 45, 90, 135,180, 225, 270, 315) * 8 points, circle amplitude = 122.1% (35.3, 54.7, 125.3, 144.7, 215.3, 234.7, 305.3, 324.7) * 4 points, circle amplitude = 141.4% (45, 135, 225, 315) Note: The 100% values correspond to typically 21700 digits and a voltage of ~ 110 mV.
Table 17 Register Bits 000 001 010 011 100 101 110 111
1)
Functional Angle Test X / Y Values (decimal) min. -400 14800 20700 typ. 0 15500 21700 32767 0 -15500 -21700 -32768 max. 400 16200 22700 400 -16200 -22700
1)
-400 -14800 -20700
Not allowed to use.
Preliminary Data Sheet
45
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TLE5010
Draft ADC Test Vectors Test Structures
Y
122.1% 141.4%
0%
100.0% 70.7%
X
Figure 14
ADC Test Vectors
11.2
Temperature Measurement
An internal bandgap voltage can be used to measure the temperature on the chip. This may be used to compensate temperature dependent errors. The temperature value is sent out instead of the X value. Table 18 Parameter Value at -40C Value at 25C Value at 150C Temperature Sensitivity
1)
Temperature Measurement Symbol Limit Values min. typ. +5775 -188.75 max. +22000 digits +9000 digits digits dig / K
1)
Unit
Notes
T-40 T25 T150 ST
+2550 -
-22000 -
Should be used for temperature compensation of offset errors
Preliminary Data Sheet
46
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TLE5010
Draft Test Structures
11.3
Angle Test and Temperature Measurement Timing
The angle test and the temperature readout is based on the same mechanism. In the Normal Mode, the output path is linked to the angle test or temperature measurement unit until the mode is terminated.
< tupd tupd FSYNC (reset) FCNT[4] ADC&Filter X[16],Y[16] Buffer1 ANGT_EN or TEMP_EN Update GMR_OFF 4 Val_G4 Val_G3 5 Val_G5 0 Val_A0 1 Val_A1 Val_A0 tupd tupd
< tupd tupd tupd tupd
2 Val_A2
0 Val_G0
1 Val_G1 Val_G0
2 Val_G2 Val_G1
Val_G4
Val_A1
useful No GMR signal available
Figure 15
Measurement in Normal Mode
In the Automatic Mode, the signal is automatically switched back to GMR measurement after the read-out of one value.
< tupd tupd FSYNC (reset) FCNT[4] ADC&Filter X[16],Y[16] Buffer1 ANGT_EN or TEMP_EN Update GMR_OFF No GMR signal available automatic! 4 Val_G4 Val_G3 5 Val_G5 0 Val_A0 1 Val_A1 Val_A0 tupd tupd tupd Updated FCNT=2 0 Val_G0 Val_A1 1 Val_G1 Val_G0 2 Val_G2 Val_G1 tupd tupd
Val_G4
Figure 16
Measurement in Automatic Mode
47 V 0.9, 2007-05
Preliminary Data Sheet
TLE5010
Draft Overvoltage Comparators
12
Overvoltage Comparators
Various comparators monitor the voltage in order to ensure a error free operation. The overvoltages must be active for at least tDEL to set the test comparator bits in the SSC Interface registers. This works as digital spike suppression.
Table 19 Parameter
Overvoltage Detection
Test Comparators Symbol Limit Values min. typ. max.
V V V V V V s 2.80 2.80 2.80 6.5 0.54 0.48 10 -
Unit
Notes
VOVG VOVA VOVD VDD Overvoltage VDDOV GND - Off Voltage VGNDoff VDD - Off Voltage VVDDoff
Spike filter Delay
VGND_OFF = VGND - VTST1 VVDD_off = VCLK - VDD or VSCK - VDD
The error condition has to be longer than this value (min. 256 clocks of fDIG)
tDEL
12.1
Internal Supply Voltage Comparators
Every voltage regulator has an overvoltage comparator to detect a malfunction. If the nominal output voltage of 2.5 V is larger than VOVG, VOVA and VOVD, then this overvoltage comparator is activated. It sets the VRx_OV bit.
.
VDDA REF VDD VRG VRA VRD GND
+
GND
10s Spike Filter
xxx_OV
Figure 17
OV Comparator
12.2
VDD Overvoltage Detection
This comparator (see Figure 17) monitors the external supply voltage at the VDD pin. It activates the STAT_VR bit.
Preliminary Data Sheet 48 V 0.9, 2007-05
TLE5010
Draft Overvoltage Comparators
12.3
GND - Off Comparator
This comparator is used to detect a voltage difference between the GND pin and TST1 (which must be soldered to GND in the application). It activates the STAT_VR bit. This circuit can detect a disconnection of the Supply GND Pin.
.
VDD VGNDoff TST1 +dV
VDDA
+
GND
GND
10s Spike Filter
GND_OFF
Figure 18
GND - Off Comparator
12.4
VDD - Off Comparator
This comparator detects a disconnection of the VDD pin supply voltage. In this case the TLE5010 is supplied by the SCK, CLK and CS input pins via the ESD structures. It activates the STAT_VR bit. The retriggerable analog monoflop is necessary because of the not static signal of the CLK and SCK signals. This comparator is also activated, if spikes on CLK or SCK achieve the condition: (VCLK - VDD) > VVDDoff or (VSCK - VDD) > VVDDoff
.
VDDA VDD VVDDoff CLK SCK GND -dV
+
GND
1s Mono Flop
10s Spike Filter
VDD _OFF
Figure 19
VDD - Off Comparator
Preliminary Data Sheet
49
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TLE5010
Draft Typical Application Circuit
13
Typical Application Circuit
The application circuit shows the C version with open drain capabilities.
12V Voltage Regulator
VDD
SSC
CLK DATA_o
each 100R
1k VDD 100R
CAN RX CAN TX
CAN Tranceiver
CAN
Controller Master
DATA_i SCK CSQ
GMR-Sensor TLE5010
GND
100nF
GND
Figure 20
Application Circuit
13.1
Angle Sensor System
A complete system may consist out of one TLE5010 and a micro controller. The second TLE5010 can be redundand in order to increase the system reliability. The C should contain a CORDIC coprocessor for fast angle calculations and a flash memory for the calibration data storage.
Preliminary Data Sheet
50
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TLE5010
Draft Package Information
14
14.1
Table 20 Parameter
Package Information
Package Parameters
Package Parameters Symbol Limit Values min. typ.
150 MSL 3 Cu194 / OLIN
Unit max.
200 75 85 K/W K/W K/W
Notes
Junction to Air 1) Junction to Case Junction to Lead 260C Fe 2.35%, P 0.03%, Cu 97.5%, Zn0.12% stamped > 7 m Halogen Free
Thermal Resistance RthJA
-
RthJC RthJL
Soldering Moisture Level Lead frame
Plating Molding Compound
1)
Sn 100% EME-G700
according to Jedec JESD51-7
Preliminary Data Sheet
51
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TLE5010
Draft Package Outline PG-DSO-8 Package Information
0.1 MIN. STAND OFF
A
1.65 0.1
0.33 0.08 x 45
1.22 0.18
D
4.9 0.08
3.9 0.11)
E
0.2 -0.01
+0.05
1.27 0.41 +0.1 -0.05 2.53
(1.5)
C 0.1 8x D C 8x SEATING PLANE
0.64 0.25 6 0.2
0.2
M
0.4 B
3 x 1.27 = 3.81
1.95 0.32 MIN.
Detail A
o0.6 Sensitive Area 2)
3)
Center of Sensitive Area Pin 1 Index Marking
8
5
1
4
B
5.06 0.1
1) Does not include plastic or metal protrusion of 0.15 max. per side 2) Max. 3 tilt of sensitive area to preference "E" 3) Independent from dimensions 1.65 and 1.22 GPS19032
Figure 21
Package Outline PG-DSO-8
Preliminary Data Sheet
0.4 A
52
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8MAX.
A
TLE5010
Draft Footprint PG-DSO-8 Package Information
1.31
0.65 5.69 1.27
Figure 22 Packing
Footprint PG-DSO-8
8
0.3
12 0.3
5.2
6.4
1.75 2.1
Figure 23
Tape and Reel
Preliminary Data Sheet
53
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TLE5010
Draft Marking Package Information
Top view
Bottom view
123456
G 0624
Pin 1 marking
Type code Date code (Year/Month) Green Package
111111 11111 111111 Pin 1 Production Code
HLGM1227
Figure 24
Marking
Processing
For processing recommendations please refer Infineon's "Notes on Processing"
Preliminary Data Sheet
54
V 0.9, 2007-05
TLE5010
Draft Package Information
Preliminary Data Sheet
55
V 0.9, 2007-05
www.infineon.com
Published by Infineon Technologies AG

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